A comparison of incomplete LU-factorisation in semiconductor device simulation

Stefan Röllin

Email: roellin@iis.ee.ethz.ch
Postal address: Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, 8092 Zurich, Switzerland

The solution of sparse linear systems is an important task in numerical simulations in computational science and engineering.  In semiconductor device simulation the physical and electrical behaviour of semiconductor devices is investigated. There is a steadily growing demand to carry out 3D simulations. Only advanced device structures in 3D combined with a fine simulation mesh are able to describe the complex devices and to resolve the relevant physical effects. Such simulations lead to huge sparse linear systems that pose high requirements on the solver. Only iterative solvers are suited for those systems due to time and memory constraints.

An iterative solver for large sparse linear systems consists of different ingredients. For example unsymmetric permutations and scalings aimed at placing large entries on the diagonal greatly enhance the reliability of iterative solvers. Symmetric permutations reduce the fill-in of a preconditioner. The heart of an iterative solver is a Krylov subspace method such as BiCGstab or GMRes. But of utmost importance is a suitable preconditioner that speeds up the convergence significantly. 

There are a lot of different preconditioners known in the literature. The most effective and most robust problem-independent preconditioning techniques are probably incomplete LU-factorisations. The topic of this talk is to compare such ILU-factorisations for semiconductor device simulations. In particular, the focus lies on multilevel ILU-methods (from ILUPACK) that are the most recent variants of incomplete factorisations and one expects that they are more robust than older, simpler versions. We will clarify which incomplete factorisation performs best and which one is the most robust one in the mentioned field.